Rushby : Formal Verification for Time - Triggered Algorithms

An Overview of Formal Verification for the Time-Triggered Architecture

We describe formal verification of some of the key algorithms in the Time-Triggered Architecture (TTA) for real-time safety-critical control applications. Some of these algorithms pose formidable challenges to current techniques and have been formally verified only in simplified form or under restricted fault assumptions. We describe what has been done and what remains to be done and indicate s...

Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms

Many critical real-time applications are implemented as time-triggered systems. We present a systematic way to derive such time-triggered implementations from algorithms specified as functional programs (in which form their correctness and fault-tolerance properties can be formally and mechanically verified with relative ease). The functional program is first transformed into an untimed synchro...

Formal Verification for Fault - Tolerant Architectures and the Design Of

Formal Specification and Verification of a Fault-Masking and Transient-Recovery Model for Digital Flight-Control Systems

Expanded Version of a Paper from the Sixth Working Conference on Dependable Computing for Critical Applications, Systematic Formal Veriication for Fault-tolerant Time-triggered Algorithms

Many critical real-time applications are implemented as time-triggered systems. We present a systematic way to derive a time-triggered implementation from a fault-tolerant algorithm speciied as a functional program. It is relatively easy to formally and mechanically verify correctness and fault-tolerance properties of algorithms expressed in this latter form. The functional program is next tran...